The present application relates to semiconductors, and more specifically, to techniques for forming vertical field-effect transistor semiconductor structures. Fin field-effect transistor (FinFET) devices include a transistor architecture that use fins as channel regions. FinFET devices may include fins with source/drain regions on lateral sides of the fins, so that current flows in a horizontal direction (e.g., parallel to a substrate) between source/drain regions at opposite ends of the fins in the horizontal direction. Vertical transport field-effect transistor (vertical FET or VFET) devices include source/drain regions at ends of the fins on top and bottom sides of the fins, so that current flows in a vertical direction (e.g., perpendicular to the substrate) from a bottom source/drain region to a top source/drain region. Vertical FET devices address limitations in scaling of horizontal FET devices, such as by decoupling gate length from contact gate pitch. Therefore, vertical FET devices are viable options for continued scaling of complementary metal-oxide-semiconductor (CMOS) devices.